The present invention relates to a storage device and relates in particular to control for accessing storage areas shared among multiple disk controllers (DKC) containing cache memories in storage systems.
Current high-performance computer systems contain large-capacity secondary storage devices. Data required by the host device such as the CPU (central processing unit) is stored in the secondary storage device and is written into or read from the CPU (or other device) whenever needed. An nonvolatile storage medium is generally used as the secondary storage device. Typical secondary storage devices, for example, are disk devices such as magnetic disk devices or optical disks, etc.
In recent years, higher performance is being required of these disk devices due to advances in information processing. In response to higher performance, disk devices in particular need higher data input/output throughput and more disk drive units must be connected.
One method for improving the throughput in disk devices is to connect multiple disk controllers to a disk array, and to increase the number of ports connecting the host device with the cache memory capacity of the disk device.
One disk device of this type is disclosed for example in Japanese Published Unexamined Patent Application No. 2001-344188 wherein a disk array device with multiple disk drives shared among multiple controllers. This disclosed related art is hereinafter called the First related art.
Another method of the related art attempted in particular to increase the number of connected disk drive units is by means of the switch connection at the disk array connections to the disk controller within the disk device.
A switch for this type of switching connection is disclosed for example in Japanese Published Unexamined Patent Application No. 2003-196140. In this technology, the switch for accessing the storage area shared among multiple computers connected to that switch is an exclusive access control switch. Moreover, when a mismatch has occurred in the write-through cache memories within the multiple computers, the switch sends an instruction to the computers to invalidate the mismatch data. This disclosed related art is hereinafter called the Second related art.
FIG. 19 is a block diagram of the disk device of the related art containing multiple disk controllers. The disk device in FIG. 19 is made up of two units; two disk controllers DKC0, DKC1 and a disk array DA. The disk controller structure is described using DKC0 as an example. The disk controller DKC0 is made up of a channel adapter CHA0 for connecting the host CPU (not shown in drawing) with the disk device, a cache memory CM0 for temporarily storing the data to read and write on the disk array DA, and a disk adapter DKA0 for connecting the disk controller DKC0 and the disk array DA. A bus or a switch interconnects the channel adapter CHA0, and the cache memory CM0 and the disk adapter DKA0. The channel adapter CHA0 connects to the CPU via a channel C00. The disk adapter DKA0 connects to the disk array DA via a channel D00.
The write data inputted from the host CPU via the channel C00 is temporarily stored in the cache memory CM0. When the cache memory operation is set in the write-back, the disk controller DKC0 informs the host device that writing is complete when the write data has been stored in the cache memory. The disk controller DKC0 later sends the write data stored in the cache memory CM0 from the disk adapter DKA0 to the disk array DA via the channel D00.
When reading data, a check is made first of all whether the data is stored within the cache memory CM0. If the data is present, the stored data within the cache memory is sent from the cache memory CM0 via the channel adapter CHA0, to the host CPU. If there is no matching data within the cache memory CM0, the disk adapter DKA0 reads data from the disk array DA by way of the channel D00. The disk adapter DKA0 sends this read data via the channel adapter CHA0 to the host CPU. The disk controller DKC1 is made up of a channel adapter CHA1, a cache memory CM1, and a disk adapter DKA1, the same as the disk controller DKC0. The disk controller DKC1 is connected via channel C10 to the CPU (not shown in drawing) and connects to the disk array by way of a channel D10. The operation is the same as that of the disk controller DKC0.
The case where the disk array DA contains a shared volume is assumed next. The shared volume is a disk area capable of being commonly accessed from the multiple disk controllers. In the example in FIG. 19, the shared volume is a disk area capable of reading and writing (data) from either the disk controller DKC0 and DKC1.
One of the main problems with using this shared volume is that exclusive access control prohibits simultaneous writing by multiple disk controllers. Multiple disk controllers simultaneously writing on the same disk area might disable the data writing by any of the controllers so exclusive access control of writing onto the shared volume is required.
Another problem is maintenance of coherency (matching) among the cache memories within the multiple controllers. A cache memory mismatch may be considered as the following state. For example, when the disk controller DKC0 writes on the shared volume, the most recent data is stored inside the cache memory CM0 within the disk controller DKC0. However, that data is not stored within the cache memory CM1 inside the disk controller DKC1 so that a data mismatch occurs in the cache data of the area corresponding to the shared volume of the cache memory CM0 and the cache memory CM1.
An exclusive access control part is installed in each disk controller in the disk array device of the First related art. Signal lines for exclusive access control between each disk controller and for cache coherency control are installed between each disk controller. However, when there are an increased number of disk controllers accessing the shared volume, this method for installing exclusive access control parts in each of the disk controllers makes control more complex and causes higher costs because a larger number of parts are used.
No consideration was ever given in this storage system, to connecting a switch between the multiple disk controllers and the disk array, and using this switch to control the shared volume commonly used by the multiple disk controllers.
When the switch of the second related art is utilized to connect with the multiple disk controllers with the disk array, the exclusive access control is easier than in the first related art because exclusive access control by the switch is concentrated. However, consideration was only given to using the write-through type of cache memory for coherency control of the cache memory. Therefore, when using the method of the second related art, it is impossible to apply coherency (match) control in cache memories for disk controllers using the normal write-back method. The coherency control for the cache memory of the second related art discloses a method for invalidating non-matching data. However no method is disclosed for matching data among the cache memories.